The present invention generally relates to a method for fabricating a semiconductor structure and more particularly, relates to a method for forming a TiN layer on a metal silicide layer in a semiconductor structure and a structure formed by the method.
In CMOS structures, silicides (TiSi2 or CoSi2) are used as contacts to the active regions as well as for conductive paths between regions of separate devices. In the contact region, a barrier is normally deposited on the silicide in a contact hole to prevent metal and Si inclusion to F attack during the subsequent W deposition from WF6. A barrier layer can be formed by depositing Ti on top of the silicide (CoSi2) at the bottom of the contact hole and annealing in N2/H2 or NH3 gas at a temperature between 550xc2x0 C. and 600xc2x0 C. to ensure the formation of a TiN or TiON barrier on top of the silicide.
In order to get enough Ti into the bottom of the hole (on top of silicide) of the contacts with higher aspect ratios, ionized metal plasma (IMP) deposition is used. A thick Ti film on top of the silicide ensures better coverage of the barrier layer and reduces the chance of any pin hole in the barrier. However, it was discovered that when a thick (30-60 nm) Ti layer was deposited on top of the silicide layer and annealed at temperatures above 500xc2x0 C., Ti reacted with CoSi2 to form an amorphous material between TiON and COSi2. The amorphous material contains primarily Ti, Co and Si. The weakly bonded Ti in the amorphous layer can react with fluorine inxe2x80x94WF6 during the CVD W deposition and form a volatile compound. This volatile compound causes a volume expansion and subsequently results in a barrier liner rupture. The liner rupture exposes the silicide to F attack during CVD WF6 deposition. This failure mechanism results in an electric open in the W studs.
In addition to the reaction with fluorine, the thick amorphous layer between TiON and CoSi2 also causes consumption of silicon, which results in a shifting of the silicide layer deeper into the P-well or N-well. The shifting of silicide in to the P or N-well could cause junction leakage.
Due to the consequences of the reaction between F and the amorphous material that contains Ti, Co and Si, it is desirable to either eliminate the formation of the amorphous material layer or to reduce the thickness of the amorphous layer in order to decrease the risk of fluorine attack. TEM (Transmission Electron Microscopy) results on a n as-deposited 35 nm thick Ti film on CoSi2 after various annealing treatments in forming gas indicated that a 6 nm thick amorphous layer is produced after annealing at 550xc2x0 C. for 30 min, while an 8 nm thick amorphous layer is obtained after annealing at 600xc2x0 C. for 30 min. For the 550xc2x0 C. anneal, the TEM image further shows that Ti amorphizes the top surface of CoSi2 to form a Tixe2x80x94Coxe2x80x94Si layer. Neither of these thicknesses, i.e. 6 nm or 8 nm, is acceptable in a high aspect ratio CMOS device. In-situ x-ray diffraction results were obtained on as-deposited 35 nm Ti on CoSi2 films after various annealing treatments in purified N2. The data indicates a thickness reduction in CoSi2 in contact with Ti as the temperature is increased during N2 annealing treatments. This result is consistent with the TEM results which show an increased amorphous layer thickness after annealing.
Referring initially to FIG. 1, wherein a semiconductor structure 10 is prepared by a conventional method is shown. In structure 10, a silicon substrate 12 is shown. A native oxide layer 14 is formed on the surface of a metal silicide layer 16 of, for instance, cobalt silicide before the deposition of a titanium layer 18.
The as-deposited structure 10 is annealed using a conventional annealing method to produce the structure shown in FIG. 2. After single-step annealing at a high temperature between about 550xc2x0 C. and about 600xc2x0 C. for 30 min, on top of the metal silicide layer 16, a thick amorphous material layer 20 of Tixe2x80x94Sixe2x80x94Co nitrogen is formed. On top of the amorphous material layer 20, a Tixe2x80x94Oxe2x80x94N layer 22 is formed. The amorphous material layer 20 formed at a high temperature, i.e. at a temperature higher than 500xc2x0 C., may have a thickness more than 5 nm, and more likely a thickness between about 5 nm and about 10 nm, as shown in FIG. 5.
It is therefore an object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer that does not have the drawbacks or the shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by a suitable annealing process.
It is a further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure that produces an amorphous material layer of Tixe2x80x94Coxe2x80x94Si that has a minimum thickness.
It is another further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by annealing the structure in a dual-step annealing process.
It is still another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by first forming a sub-stoichiometric TiN at a lower annealing temperature and then forming a stoichiometric TiN layer at a higher annealing temperature.
It is yet another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by annealing the structure in a dual-step annealing process consisting of a first step of low temperature annealing at 500xc2x0 C., and then a second step of high temperature annealing at 600xc2x0 C.
It is still another further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure that forms a by-product amorphous material layer of Tixe2x80x94Coxe2x80x94Si having a thickness of less than 5 nm.
It is yet another further object of the present invention to provide a semiconductor structure that has a TiN layer formed on top of a metal silicide layer which includes an amorphous layer of Tixe2x80x94Coxe2x80x94Si of less than 5 nm.
In accordance with the present invention, a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and a structure formed by the method are disclosed.
In a preferred embodiment, a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure can be carried out by the operating steps of first providing a semiconductor structure that has a metal silicide layer on top, depositing a Ti layer on top of the metal silicide layer, depositing a nitrogen-containing Ti layer on top of the Ti layer, heating the semiconductor in a forming gas or nitrogen containing environment to a first temperature not higher than 500xc2x0 C. for less than 2 hours, and heating the semiconductor structure in an N2-containing gas to a second temperature not lower than 500xc2x0 C. for less than 2 hours to form the TiN layer.
In the method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure, the metal silicide is a member selected from the group consisting of cobalt disilicide, nickel monosilicide, titanium disilicide, tungsten disilicide, tantalum disilicide and niobium disilicide. The ambient gas may be a gas selected from the group consisting of N2, NH3, N2/H2. The method may further include the step of heating the semiconductor structure at a first temperature between about 300xc2x0 C. and about 500xc2x0 C., and heating the semiconductor structure at a second temperature between about 500xc2x0 C. and about 800xc2x0 C. The method may further include the step of heating the semiconductor structure at a first temperature preferably between about 450xc2x0 C. and about 500xc2x0 C., and heating the semiconductor structure at a second temperature preferably between about 600xc2x0 C. and about 650xc2x0 C. The method may further include the step of heating the semiconductor structure at a first temperature of about 500xc2x0 C., and then at a second temperature of about 600xc2x0 C.
The method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure may further include the step of heating the semiconductor structure at the first temperature for between about 15 min and about 45 min, or the step of heating the semiconductor structure at a second temperature for between about 15 min and about 45 min. The method may further include the step of heating the semiconductor structure at the first temperature for about 30 min, and heating the semiconductor structure at the second temperature for about 30 min. The method may further include the steps of forming a sub-stoichiometric TiN as a top layer at the first temperature, and forming a stoichiometric TiN layer at the second temperature.
The present invention is further directed to a semiconductor structure that has a TiN layer formed on top of a metal silicide layer which includes a semiconductor structure that has a metal silicide layer on top, an amorphous layer containing Si, Ti and Co of less than 5 nm thick on top of the metal silicide layer, and a TiN layer on top of the amorphous layer.
In the semiconductor structure that has a TiN layer formed on top of a metal silicide layer, the metal silicide is a member selected from the group consisting of cobalt disilicide, nickel monosilicide, titanium disilicide, tungsten disilicide, tantalum disilicide and niobium disilicide. The semiconductor structure may be a CMOS. The TiN layer is a stochiometric TiN formed after annealing at 600xc2x0 C. for 30 min. The amorphous layer may have a thickness of about 3 nm.